Integrated circuits often employ electrostatic discharge protection to prevent damage to electronic devices during an electrostatic discharge event. Such protection may prevent damage from high voltage or current transients, including those that may occur during installation. Metal oxide semiconductor (MOS) integrated circuits are particularly vulnerable to electrostatic discharge because an electrostatic discharge event may melt the silicon or damage gate oxides and/or the short channel devices used in their design. Designing integrated circuits into deep sub-micron scale presents challenges to traditional forms of electrostatic discharge protection.
One prior approach used for electrostatic discharge protection employs a lateral NPN transistor formed by an n-channel MOSFET (NMOS) or field oxide device between the input pad and a substrate closely coupled to ground. The device is used to shunt to ground the large transient current caused by an electrostatic discharge event by turning on the lateral NPN when an event occurs. This approach may also utilize a vertical PNP transistor with a collector common to the substrate to trigger forward biasing of the lateral NPN transistor. When placed near the lateral NPN transistor, the vertical PNP transistor may lower the trigger voltage of the lateral NPN by raising the local substrate potential near the base of the lateral NPN transistor.
This prior approach may not be particularly effective in deep sub-micron products, such as those utilizing silicided CMOS technology. Silicided CMOS products generally have low substrate resistance and often encounter problems with uniform turn-on, and even failure, of the lateral NPN transistor. This approach may also not be particularly advantageous for mixed signal products, where chip capacitance is normally substantially smaller. In such products, large substrate current injection may be desirable to bias the substrate near the lateral NPN transistor. Larger circuit area, not usually available in modern sub-micron designs, may be used to achieve such current injection. Furthermore, the vertical PNP trigger may become de-biased at these chip capacitances. Therefore, a suitably-sized device resistant to de-biasing is needed to provide relatively uniform current injection into the substrate, to activate the lateral NPN transistor.